Encoder interpolation circuit which corrects an interpolation angle between a received sine-wave encoder signal and a cosine-wave encoder signal

ABSTRACT

An encoder interpolation circuit for obtaining interpolation data within one wave from two sine-wave encoder signals of different phases comprises interpolative computation means ( 2 ) for receiving two sine-wave encoder signals received and carrying out to interpolative computation within one wave, signal deviation detecting means ( 3 ) for detecting a deviation of the two sine-wave encoder signals, correction data forming means ( 4 ) for outputting correction data corresponding to the detected deviation and the output of the interpolative computation means, and corrective computation means ( 5 ) for obtaining the corrected interpolation data by carrying out corrective computation for the output of the interpolative computation means with the correction data and obtaining corrected interpolation data.

TECHNICAL FIELD

The present invention relates to an interpolation circuit forinterpolating detection signals from an encoder for to thereby detectrotational angles or positions on a straight line.

BACKGROUND ART

In a detecting device for detecting positions of a table and a motor ofa machine tool of an NC apparatus, a rotary-type pulse encoder attachedto the motor shaft or the like and a linear-type pulse encoder attachedto a worktable or the like are known as means for detecting the movementand moving speed of a moving body. As the moving body moves, theseencoders generate an A-phase signal, a sine-wave signal (Ksin θ), and aB-phase sine-wave signal (Ksin(θ±π/2)), which has a phase difference of90° from the A-phase signal, and obtains angle data (θ) by carrying outinterpolative computation with use of these two sine-wave signals,thereby improving the resolution for the position and speed.

There are known methods for this interpolation technique, including amethod in which a converter circuit for sine- and cosine-wave signalsfrom a signal source is composed of a plurality of resistors andcomparator arrays. In another method based on the interpolation circuitconfiguration shown in FIG. 15, a sine-wave signal V_(A) and acosine-wave signal V_(B) are inputted to the interpolative computationunit 2 after being A/D-converted by unit of A/D converters 1 a and 2 a,respectively, and the interpolative computation unit 2 computestan⁻¹(V_(A)/V_(B)) to obtain angle data θ. The computation of thisinverse transform of a tangent can be carried out by using a calculationprocess based on a Taylor expansion, for example.

An interpolation circuit used for a conventional encoder carries outinterpolative computation on the assumption that it receives an A-phasesignal (sine-wave signal) and a B-phase signal (cosine-wave signal) thatare equal in amplitude K and have a phase difference of π/2.

In general, however, A- and B-phase signals that are inputted to anencoder do not always have an accurate phase difference of π/2, and arenot always equal in amplitude. In other words, the phase differencebetween the two signals may be deviated from π/2 or the amplitude ratiomay be deviated from 1.

If interpolative computation is carried out with use of these deviatedsignals, the obtained angle θ may possibly be subject to aninterpolation error attributable to the deviation.

Conventionally, therefore, this interpolation error is removed by amethod in which an analog regulator circuit is provided in front of A/Dconverters so that the amplitude ratio between the A- and B-phasesignals inputted to the analog regulator circuit can be adjusted to 1 orthat phase difference between the A- and B-phase signals can be adjustedto π/2.

However, the removal of the interpolation error by means of the analogregulator circuit requires a complicated circuit configuration. Sincethe regulator circuit is an analog circuit, moreover, it is necessary toadjust the regulator circuit itself.

DISCLOSURE OF THE INVENTION

The object of the present invention is to provide an interpolationcircuit for an encoder, in which interpolation data cleared of aninterpolation error that is attributable to signal deviations can beobtained by correcting interpolation data, which is obtained byinterpolative computation, without adjusting input signals.

In order to achieve the above object, an encoder interpolation circuitaccording to the present invention comprises:

interpolative computation means for receiving two encoder signals ofdifference phases, carrying out interpolative computation for thesesignals and outputting interpolation angle data, correction data formingmeans for obtaining and outputting correction data corresponding to acombination of a detected deviation of the two encoder signals from anormal waveform and the interpolation angle data outputted from theinterpolative computation means; and corrective computation means forcorrecting the interpolation angle data outputted from the interpolativecomputation means with the correction data outputted from the correctiondata forming means and outputting corrected interpolation angle data.

Preferably, the deviation of the two encoder signals is the ratio of theamplitude of one sine-wave encoder signal to the amplitude of the othersine-wave encoder signal.

Preferably, the deviation of the two encoder signals is a phase error asthe difference between the predetermined a phase difference between twoencoder signals and an actual phase difference between the two encodersignals.

Preferably, the correction data forming means forms the correction databy substituting an output of the interpolative computation means and adetected phase error, as a deviation of the two encoder signals,individually for variables in a computational expression for obtainingpreset correction data and operating the computational expression.

Preferably, the correction data forming means is previously stored withthe value of correction data for a combination of the output of theinterpolative computation means and the output of the correction dataforming means, and the correction data forming means receives the outputof the interpolative computation means and the output of the correctiondata forming means and outputs the correction data corresponding to thecombination of these outputs.

Preferably, the correction data stored in the correction data formingmeans can be fetched with an address which represents a combination ofthe output of the interpolative computation means and the output of thecorrection data forming means.

Further preferably, the correction data forming means is stored with adata table so that corresponding data can be fetched with an addresswhich represents a combination of angle data in a limited range and adetected signal deviation, and the correction data forming meansincludes means for receiving the detected deviation of the two encodersignals and the output of the interpolative computation means, anddetermining an address based on the deviation and the output, and meansfor forming the correction data by accessing said data table to fetchthe corresponding data with the determined address and processing thefetched data.

According to the present invention, interpolation data cleared of aninterpolation error that is attributable to signal deviations can beobtained by correcting interpolation data, which is obtained byinterpolative computation, without adjusting input signals.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram for illustrating an outline of an encoderinterpolation circuit according to the present invention;

FIG. 2 is a block diagram for illustrating an encoder interpolationcircuit according to a first embodiment of the present invention;

FIG. 3 is a block diagram for illustrating an encoder interpolationcircuit according to a second embodiment of the present invention;

FIG. 4 is a diagram for illustrating an amplitude ratio between twoencoder signals;

FIG. 5 is a diagram for illustrating an error included in interpolationdata when the amplitude difference between the two encoder signals isdeviated from π/2;

FIG. 6 is a diagram schematically showing a pattern of an error includedin computed interpolation data as the amplitude ratio between the twoencoder signals is deviated from 1;

FIG. 7 is a block diagram for illustrating elements constitutingcorrection data storage means in the encoder interpolation circuit ofFIG. 3;

FIG. 8 is a diagram schematically showing correction data patterns forcanceling the error shown in FIG. 6, according to the amplitude ratio;

FIG. 9 is a block diagram for illustrating an encoder interpolationcircuit according to a third embodiment of the present invention;

FIG. 10 is a block diagram for illustrating an encoder interpolationcircuit according to a fourth embodiment of the present invention;

FIG. 11 is a diagram for illustrating phase errors between two encodersignals;

FIG. 12 is a diagram schematically showing a pattern of an errorincluded in computed interpolation data as the phase difference betweenthe two encoder signals is deviated from π/2;

FIG. 13 is a block diagram for illustrating elements constitutingcorrection data storage means in the encoder interpolation circuit ofFIG. 10;

FIG. 14 is a diagram schematically showing correction data patterns forcanceling the error shown in FIG. 12 according to the error attributableto the phase difference; and

FIG. 15 is a diagram for illustrating a conventional encoderinterpolation circuit.

BEST MODE FOR CARRYING OUT THE INVENTION

[Outline of Encoder Interpolation Circuit]

Referring first to the block diagram of FIG. 1, an outline of aninterpolation circuit for an encoder according to the present inventionwill be described.

One encoder signal (A-phase signal; sine-wave signal) V_(A) and anotherencoder signal (B-phase signal; cosine-wave signal) V_(B) having thesame amplitude as and a phase difference of 90 degrees from V_(A) areconverted from analog signals into digital signals by A/D converters 1 aand 1 b, respectively. The A-phase signal V_(A) and the B-phase signalV_(B), converted into the digital signals by the A/D converters 1 a and1 b, are inputted to the interpolative computation means 2. Theinterpolative computation unit 2 computes

θ′=tan⁻¹(V_(A)/V_(B)),

and outputs interpolation data θ′. The interpolation data θ′ includes anerror (interpolation error δθ) that depends on a deviation in amplitudebetween the A-phase signal V_(A) and the B-phase signal V_(B) or adeviation in phase difference.

The A-phase signal V_(A) and the B-phase signal V_(B), converted intothe digital signals by the A/D converters 1 a and 1 b, are also inputtedto the signal deviation detecting unit 3, whereupon deviations(differences in amplitude or phase) between the A-phase signal V_(A) andthe B-phase signal V_(B) are detected.

Correction data forming unit 4 receives the output (interpolation dataθ′) of the interpolative computation unit 2 and the output of the signaldeviation detecting unit 3, and obtains correction data Δθ from thesedata.

Receiving the output θ′ of the interpolative computation unit 2 and theoutput Δθ of the correction data forming unit 4, corrective computationmeans 5 calculates

θ=θ′+Δθ,

and outputs interpolation data θ that includes no interpolation error.

[Case in which the signal deviation between the A- and B-phase signalsV_(A) and V_(B) is detected by the amplitude difference between the twosignals]

Referring now to FIGS. 2 to 8, there will be described a case in which asignal deviation to be detected by the signal deviation detecting unit 3of FIG. 1 is the amplitude difference between the A-phase signal V_(A)and the B-phase signal V_(B), specifically.

(First Embodiment)

Referring now to the block diagram of FIG. 2, there is explained a firstembodiment of the encoder interpolation circuit for this case. Theencoder interpolation circuit shown in the block diagram of FIG. 2 hasthe same configuration as the encoder interpolation circuit shown in theblock diagram of FIG. 1, except that, in this embodiment, the signaldeviation detecting unit 3 of the encoder interpolation circuit shown inthe block diagram of FIG. 1 is replaced with the amplitude ratiodetecting unit 3k. Accordingly, description of other components than theamplitude ratio detecting unit 3k in the encoder interpolation circuitof FIG. 2 will be omitted. The interpolative computation unit 2 receivesthe respective outputs of the A/D converters 1 a and 1 b, that is, theA-phase signal V_(A) and the B-phase signal V_(B) converted into thedigital signals, and executes interpolative computation within one wave(section from 0 to 2π).

Referring now to FIG. 4, an amplitude ratio k between the two encodersignals V_(A) and V_(B) will be described. For simplicity ofillustration in FIG. 4, the encoder signal V_(A) as a sine-wave signaland the B-phase signal V_(B) as a cosine-wave signal are represented bya triangular wave each. It is supposed that there is an exact phasedifference of π/2 between these two encoder signals V_(A) and V_(B).However, it is supposed that the two signals V_(A) and V_(B) are notequal in amplitude.

Referring to FIG. 4, if the values of the encoder signals V_(A) at azero-cross time point for the encoder signal V_(B) are V_(AH) andV_(AL), and if the values of the encoder signals V_(B) at zero-crosstime points for the encoder signal V_(A) are V_(BH) and V_(BL), theamplitude ratio k is given by the following expressions.

If (V_(AH)−V_(AL))>(V_(BH)−V_(BL)) is given, we obtain

C_(AB)=0,

k=(V_(AH)−V_(AL))/(V_(BH)−V_(BL)).  (1)

If (V_(AH)−V_(AL))<(V_(BH)−V_(BL)) is given, we obtain

C_(AB)=1,

k=(V_(BH)−V_(BL))/(V_(AH)−V_(AL)).  (2)

In the above equations, C_(AB) is a comparison flag that indicates theresult of comparison between the respective amplitudes of the encodersignals V_(A) and V_(B). C_(AB)=0 represents the case where theamplitude of the signal V_(A) is greater than the amplitude of thesignal V_(B), while C_(AB)=1 represents the case where the amplitude ofthe signal V_(A) is smaller than the amplitude of the signal V_(B).

The amplitude ratio data k and the state of the flag C_(AB) can beobtained by monitoring the values of the A/D converters 1 a and 1 b,sampling one of the values at a time when the other of the values turnsto be zero and calculating a mean value of the sampled data.

If the amplitude ratio k between the two encoder signals V_(A) and V_(B)is 1, each of these two signals V_(A) and V_(B) is represented by onepoint on a circle that is described around the origin of a rectangularcoordinate system, as shown in FIG. 5. Thus, the value for the axis ofabscissa corresponding to the one point on the circle is V_(B), thevalue for the axis of ordinate is V_(A), and the angle of a straightline that connects this point and the origin is given as angle data θ.If the amplitude of the encoder signal V_(A) is greater than theamplitude of the encoder signal V_(B) so that k is not at 1, each ofthese signals V_(A) and V_(B) is represented by one point on an ellipse,not a circle. If the amplitude of the signal V_(A) is greater than theamplitude of the signal V_(B), as shown in FIG. 5, when the one of theencoder signals is V_(B), for example, the other of the encoder signalsis kV_(A) (k>1), not V_(A). The angle of a straight line that connectsthe one point (V_(B), kV_(A)) on the ellipse and the origin is given asthe interpolation data θ′. Inevitably, therefore, the interpolation dataθ′ is computed in accordance with the signals kV_(A) and V_(B). As shownin FIG. 5, the interpolation data θ′ includes an error (interpolationerror), δθ (=θ′−θ).

If there is exact phase difference of π/2 between the two of the encodersignals V_(A) and V_(B), that is, if the one and the other of theencoder signals V_(A) and V_(B) are sine- and cosine-wave signals,respectively, the interpolation data θ shown in FIG. 5 and theinterpolation error δθ have the relation shown in FIG. 6, for example.Referring to FIG. 6, a pattern of δθ within the range of θ=0 to π/2 isthe same as a pattern of δθ within the range of θ=π to 3 π/2. Further, apattern of δθ within the range of θ=π/2 to π is the same as a pattern ofδθ within the rangeof θ=3 π/2π to 2π. Furthermore, the pattern of δθwithin the range of θ=π/2 to π and the pattern of δθ within the range ofθ=0 to π/2 are in point symmetry with respect to a point θ=π/2.

The following is a description of the correction data Δθ for theinterpolation data θ′ that includes the interpolation error in the casewhere amplitude ratio between the sine-wave encoder signal (A-phasesignal) and the cosine-wave encoder signal (B-phase signal) is at k(≠1).

Using the A-phase signal (hereinafter designated by kV_(A)) and theB-phase signal (hereinafter designated by V_(B)), the interpolation dataθ′ that includes the interpolation error is given by

θ′=tan⁻¹(kV_(A)/V_(B)),  (3)

From the above expression (3), the following expressions are obtained.

kV_(A)/V_(B)=sin θ′/cos θ′,  (4)

V_(A)/V_(B)=sin θ′/kcos θ′.  (5)

On the other hand, the interpolation data θ that includes nointerpolation error with k=1 is given by

θ=tan⁻¹(V_(A)/V_(B)),  (6)

Accordingly, the correction data Δθ can be represented as follows:

Δθ=θ−θ′=tan⁻¹(sin θ′/kcos θ′)−θ′  (7)

The above expression (7) indicates that the correction data Δθ can beobtained from the interpolation data θ′ that includes the interpolationerror and the amplitude ratio k.

Based on the interpolation data θ′ received from the interpolativecomputation unit 2 and the amplitude ratio k received from the amplituderatio detecting unit 3k, therefore, correction data computation unit 4k1of FIG. 2 carries out computation according to the aforesaid expression(7), and obtains and outputs the correction data Δθ.

Based on the interpolation data θ′ received from the interpolativecomputation unit 2 and the correction data Δθ received from correctiondata storage unit 4k1, therefore, the corrective computation unit 5calculates

θ=θ′+Δθ,  (8)

and outputs the interpolation data θ obtained by correcting theinterpolation error δθ.

(Second Embodiment)

In the first embodiment shown in FIG. 2, the correction data Δθ isobtained by the computation of expression (7) by the correction datacomputation unit 4k1. Instead of obtaining the correction data Δθ bythis computation, however, the correction data Δθ corresponding to acombination of the input value θ′ and k may be read out after previouslystoring the correction data storage unit with the relation between theinput value (θ′, k) and the correction data Δθ corresponding to thisinput value in the form of a table.

Referring now to the block diagram of FIG. 3, there is shown an encoderinterpolation circuit according to a second embodiment, which isprovided with the aforesaid correction data storage unit in place of thecorrection data computation unit 4k1.

The encoder interpolation circuit shown in the block diagram of FIG. 3has the same configuration as the encoder interpolation circuit shown inthe block diagram of FIG. 2, except that, in this embodiment, thecorrection data computation unit 4k1 of the encoder interpolationcircuit shown in the block diagram of FIG. 2 is replaced with correctiondata storage unit 4k2. Accordingly, description of other components thanthe correction data computation unit 4k1 in the encoder interpolationcircuit shown in the block diagram of FIG. 3 will be omitted.

The correction data storage unit 4k2 is stored with correction data Δθcorresponding to combinations (k, θ′) of various amplitude ratios k andthe interpolation data θ′. The correction data storage means 4k2receives the amplitude ratios k and the interpolation data θ′ from theinterpolative computation unit 2 and amplitude ratio detecting unit 3k1,and reads out the correction data Δθ according to the address (k, θ′).

A large storage capacity is needed to load the correction data storageunit 4k2 with the correction data to cope with all the possiblecombinations of the amplitude ratios k and the interpolation data θ′.However, there is a method in which correction data can be fetched forall the possible combinations of the amplitude ratios k and theinterpolation data θ′ even if the range of the interpolation data θ′ andthe amplitude ratios k are limited to reduce the quantity of data to bestored in the correction data storage unit 4k2 correspondingly. Thefollowing is a description of this method.

As mentioned before with reference to FIGS. 5 and 6, from the pattern ofthe interpolation error δθ within the range of the interpolation dataθ=0 to π/2 (first quadrant), the pattern of the interpolation error δθwithin the range of the interpolation data θ=π/2 to π (second quadrant),the pattern of the interpolation error δθ within the range of theinterpolation data θ=π to 3π/2 (third quadrant), and the pattern of theinterpolation error δθ within the range of the interpolation data θ=3π/2to 2π (fourth quadrant) can be obtained individually. Therefore,regarding the correction data Δθ for canceling the interpolation errorδθ, it is sufficient to store only the pattern of the correction data Δθwithin the range of the interpolation data θ′ (output of theinterpolative computation unit 2)=0 to π/2 (first quadrant). Thequantity of data stored in the correction data storage unit 4 can bereduced by the storage of the correction data within this limited range.

If the value of the interpolation error δθ is small, the value of theinterpolation error δθ and the amplitude ratio k can be considered to besubstantially in proportion to each other. Accordingly, only correctiondata Δθ0 for a specific amplitude ratio k0 is stored in advance so thatcorrection data Δθn for other amplitude ratios kn can be obtained bymultiplying the correction data for the specific amplitude ratio k0 bythe percentage of the amplitude ratio. Thus, the number of amplituderatios k to be stored in the correction data storage unit 4k2 can belimited to reduce the quantity of correction data stored.

The block diagram of FIG. 7 illustrates the configuration of thecorrection data storage unit 4k2 for limiting the range of theinterpolation data θ′ and the amplitude ratios k and storing thecorrection data. The correction data storage unit 4k2 comprises anaddress converter circuit 11, correction data table 12, sign inversionselector circuit 13, and multiplier circuit 14. The address convertercircuit 11 receives the interpolation data θ′ and the comparison flagC_(AB) and forms addresses. The correction data table 12 is loaded onlywith the correction data corresponding to combinations of theinterpolation data θ′ in the limited range and the limited amplituderatios k, and the correction data are read out from the table 12 inresponse to address assignment by unit the address converter circuit 11.The sign inversion selector circuit 13 inverts the sign of the readcorrection data in accordance with the computed interpolation data θ′and the comparison flag C_(AB). The multiplier circuit 14 multiplies thecorrection data by the detected amplitude ratio k.

FIG. 8 shows the relation between the correction data Δθ and theinterpolation data θ′ represented for each amplitude ratio k. Referringto FIG. 8, each correction data Δθ has a size and sign which cancel theinterpolation error δθ based on the amplitude ratio k shown in FIG. 6. Apattern of Δθ within the range of the interpolation data θ′=0 to π/2 isthe same as a pattern of Δθ within the range of θ′=π to 3π/2. Further, apattern of Δθ within the range of θ′=π/2 to π is the same as a patternof Δθ within the range of θ′=3π/2π to 2π. Furthermore, the pattern of Δθwithin the range of θ′=π/2 to π and the pattern of Δθ within the rangeof θ′=0 to π/2 are symmetrical with respect to a point θ=π/2.Accordingly, only the patterns of Δθ within the range of θ′=0 to π/2 arestored, and the correction data within the range of the correction dataθ′=π/2 to 2π can be obtained from the patterns of Δθ within the range ofthe interpolation data θ′=0 to π/2.

Further, the correction data Δθ, which changes its size depending on theamplitude ratio k, can be considered to be substantially proportional tothe percentage of the amplitude ratio k when the amplitude ratio k islow. The correction data Δθ is stored as a representative value for thespecific amplitude ratio k, and the other amplitude ratios k can beobtained by multiplication.

FIG. 8 illustratively shows cases for k=1.0, k=1.02, k=1.04, and k=1.06.For example, only the correction data Δθ for k=1.02 is stored, and theother amplitude ratios k can be obtained by multiplying the correctiondata Δθ by the ratio to k=1.02 as a multiplication factor. Here k=1.0indicates that the respective amplitudes of the two encoder signals areequal.

The address converter circuit 11 is a circuit that receives the computedinterpolation data θ′ and the comparison flag C_(AB), and formsaddresses for reading out the correction data table 12. In forming theaddresses, the addresses are outputted depending on the range of theinputted interpolation data θ′ and the sign, positive or negative, ofthe comparison flag C_(AB), with 0≦θ′<π/2 as a unit, as shown in Table 1below.

The sign inversion selector circuit 13 does or does not invert the signof the data read out from the correction data table 12, depending on therange of the computed interpolation data θ′ and the sign, positive ornegative, of the comparison flag C_(AB), as shown in Table 1.

TABLE 1 Comparison Address to Sign of Output θ′ Flag C_(AB) Data TableData 0 ≦ θ′ < π/2 0 (A > B) θ′ Non-inverted 1 (A < B) π/2 − θ′ Invertedπ/2 ≦ θ′ < 0 0 (A > B) π − θ′ Inverted 1 (A < B) θ′ − π/2 Non-inverted π≦ θ′ < 3π/2 0 (A > B) θ′ − π Non-inverted 1 (A < B) 3π/2 − θ′ Inverted3π/2 ≦ θ′ < 2π 0 (A > B) 2π − θ′ Inverted 1 (A < B) θ′ − 3π/2Non-inverted

Further, the multiplier circuit 14 is a circuit that multiplies thecorrection data stored for the specific amplitude ratio k by amultiplication factor of a percentage corresponding to the currentamplitude ratio k. Table 2 below shows examples of the multiplicationfactor. The correction data is stored in advance as a reference for theamplitude ratio k=1.02, and different amplitude ratios k are obtained bymultiplication by specific multiplication factors on the basis of theamplitude ratio k=1.02 as a reference.

TABLE 2 Amplitude Ratio Multiplication K Factor 1.00 ≦ k < 1.01 0 1.01 ≦k < 1.03 1 1.03 ≦ k < 1.05 2 1.05 ≦ k < 1.07 3 1.07 ≦ k 4

In the case where the amplitude ratio k ranges from 1.03 to 1.05, forexample, the correction data for the amplitude ratio k=1.02 ismultiplied by a multiplication factor of 2. In the case where theamplitude ratio k ranges from 1.05 to 1.07, the correction data Δθ isobtained by multiplying the correction data for the amplitude ratiok=1.02 by a multiplication factor of 3.

In a method of multiplication in the multiplier circuit 14, moreover,the correction data Δθ may be obtained by determining the multiplicationfactor in a manner such that the correction data table 12 is stored withonly correction data for a specific amplitude ratio k1 in the case wherethe amplitude of the one encoder signal is greater than the amplitude ofthe other encoder signal, and the correction data is multiplied by(1−k)/(1−k1) when the detected amplitude ratio k is higher than 1 ormultiplied by —(1−k)/(1−k1) when the detected amplitude ratio k is lowerthan 1.

In a method of multiplication in the multiplier circuit 14, furthermore,the correction data Δθ may be obtained by determining the multiplicationfactor in a manner such that the correction data table 12 is stored withfirst correction data for a specific amplitude ratio k1 in the casewhere the amplitude of the one encoder signal is greater than theamplitude of the other encoder signal, and second correction data for aspecific amplitude ratio k2 in the case where the amplitude of the oneencoder signal is smaller than the amplitude of the other encodersignal, and the first correction data is multiplied by (1−k)/(1−k1) whenthe detected amplitude ratio k is higher than 1, while the secondcorrection data is multiplied by (1−k)/(1−k2) when the detectedamplitude ratio k is lower than 1.

[Case in which the signal deviation between the A- and B-phase signalsV_(A) and V_(B) is detected by the phase difference between the twosignals]

Referring now to FIGS. 9 to 14, there will be described an encoderinterpolation circuit for correcting an interpolation error based on thephase error between the two encoder signals.

(First Embodiment)

Referring to the block diagram of FIG. 9, there is shown a firstembodiment of the encoder interpolation circuit for this case. Theencoder interpolation circuit shown in the block diagram of FIG. 9 hasthe same configuration as the encoder interpolation circuit shown in theblock diagram of FIG. 1, except that, in this embodiment, the signaldeviation detecting means 3 of the encoder interpolation circuit shownin the block diagram of FIG. 1 is replaced with phase error detectingmeans 3p. Accordingly, a description of other components than the phaseerror detecting means 3p of the encoder interpolation circuit shown inthe block diagram of FIG. 9 will be omitted.

Referring now to FIG. 11, the phase error between the two encodersignals will be described. In FIG. 11, the sine- and cosine-wave signalsare simplified in the form of triangular waves and are designated byV_(A) and V_(B), respectively. Although these two encoder signals V_(A)and V_(B) are equal in amplitude, it is supposed that their phasedifference is deviated from π/2 (that is, a phase error exists).

For detecting a phase error Pd between these two encoder signals V_(A)and V_(B), a zero-cross point for the encoder signal V_(A) is selectedas a starting point and then the times t1, t2, t3, t4 and t5 at thezero-cross points for the signals are measured. Thereupon, the phaseerror Pd can be obtained as follows:

Phase difference P1={(t1+t3)/2−t2/2}/t4×2π,  (9)

Phase difference P2={(t3+t5)/2−(t2/2+t4/2)}/t4×2π,  (10)

Phase difference P=(P1+P2)/2,  (11)

Phase error Pd=P−t4/4×2π.  (12)

Although the average of the phase differences P0 and P2 is obtainedaccording to the above expression in order to improve the detectionaccuracy, the phase error may be also obtained from the phase differenceP1 only.

In obtaining the foregoing phase error Pd, measurement has to be is madein a state such that the moving speed of an object to be detected is sostable that variation in the speed during the time from t1 to t5 isnegligible. Further, the phase error is obtained by calculating a meanvalue after sampling data during a plurality of cycles of input signals.

If the two encoder signals V_(A) and V_(B) are deviated from the phasedifference of π/2 (i.e., if an error in the phase difference isproduced), the error δθ included in the interpolation data θ′ computedbased on the signals V_(A) and V_(B) has a pattern such as the one shownin the diagram of FIG. 12. FIG. 12 schematically shows the relationbetween the error δθ and real angle data θ that does not include theerror δθ. A pattern of the error δθ within the range of the angle dataθ=0 to π and a pattern of the error δθ within the range of the angledata θ=π to 2π are bisymmetrical with respect to a point θ=π.

It is supposed that the phase difference between the two encoder signalsis deviated from π/2 by Pd, so that the interpolation data θ′, deviatedfrom the real value θ by Δθ, is given when an interpolative computationis carried out for these encoder signals. In order to cancel theinterpolation error δθ, therefore, the correction data Δθ is given tothe interpolation data θ′.

In this case, the following expression is established among theinterpolation data θ′ that includes the interpolation error δθ, realangle θ, and phase error Pd:

 θ′=tan⁻¹(sin θ/cos(θ−Pd)).  (13)

Accordingly, we obtain $\begin{matrix}\begin{matrix}{{\sin \quad {\theta^{\prime}/\cos}\quad \theta^{\prime}} = {\sin \quad {\theta/\cos}\quad {\theta \left( {\theta - {Pd}} \right)}}} \\{= {\sin \quad {\theta/{\left\{ {{\cos \quad {\theta \cdot {\cos ({Pd})}}} + {\sin \quad {\theta \cdot {\sin ({PD})}}}} \right\}.}}}}\end{matrix} & (14)\end{matrix}$

From expression (14), we obtain

sin θ/cos θ=sin θ′·cos(Pd)/(cos θ′−sin θ′·sin(Pd)).  (15)

Accordingly, the real angle θ is given by the following expression:

θ=tan⁻¹{(sin θ′·cos(Pd)/(cos θ′−sin θ′·sin(Pd))}.  (16)

Based on the above expression (16), the correction data Δθ is given bythe following expression: $\begin{matrix}\begin{matrix}{{\Delta \quad \theta} = {\theta - \theta^{\prime}}} \\{= {\tan^{- 1}\left\{ {\left( {\sin \quad {\theta^{\prime} \cdot {{\cos ({Pd})}/\left( {{\cos \quad \theta^{\prime}} - {\sin \quad {\theta^{\prime} \cdot {\sin ({Pd})}}}} \right)}}} \right\} - {\theta^{\prime}.}} \right.}}\end{matrix} & (17)\end{matrix}$

The above expression (17) indicates that the correction data Δθ can beobtained from the phase error Pd and the interpolation data θ′ thatincludes the interpolation error δθ.

Thereupon, correction data computation means 4p1 of FIG. 9 carries outcomputation based on the aforesaid expression (17) in accordance withthe interpolation data θ′ received from the interpolative computationmeans 2 and the phase error Pd received from the phase error detectingmeans 3p, and obtains and outputs the correction data Δθ.

Based on the interpolation data θ′ received from the interpolativecomputation means 2 and the correction data Δθ received from thecorrection data computation unit 4p1, therefore, the correctivecomputation means 5 of FIG. 9 calculates

θ=θ′+Δθ,  (18)

and outputs the real angle, that is, the interpolation data θ, obtainedafter the correction of the interpolation error δθ.

(Second Embodiment)

In the first embodiment shown in FIG. 9, the correction data Δθ isobtained by the computation of expression (17) by unit of the correctiondata computation means 4p1. Correction data storage means 4p2 may beused in place of the correction data computation means 4p1 for thiscomputation. An encoder interpolation circuit according to this secondembodiment is shown in the block diagram of FIG. 10.

The encoder interpolation circuit shown in the block diagram of FIG. 10has the same configuration as the encoder interpolation circuit shown inthe block diagram of FIG. 9, except that, in this embodiment, thecorrection data computation unit 4p1 of the encoder interpolationcircuit shown in the block diagram of FIG. 9 is replaced with thecorrection data storage unit 4p2. Accordingly, a description of othercomponents than the correction data storage means 4p2 in the encoderinterpolation circuit of FIG. 10 will be omitted.

The correction data storage unit 4p2 is stored with correction data Δθcorresponding to combinations (Pd, θ′) of various phase errors Pd andthe interpolation data θ′. The correction data storage unit 4p2 receivesthe phase errors Pd and the interpolation data θ′ from the interpolativecomputation unit 2 and the phase error detecting unit 3p, and reads outthe correction data Δθ according to the address (Pd, θ′).

A large storage capacity is required for loading the correction data Δθso as to cope with all the possible combinations of the phase errors Pdand the interpolation data θ′. There is a method in which the correctiondata can be fetched for all the possible combinations of the phaseerrors Pd and the interpolation data θ′ even if the range of theinterpolation data θ′ and the phase errors Pd are limited to reduce thequantity of data to be stored in the correction data storage unit 4p2correspondingly. The following is a description of this method.

As shown in FIG. 12, the pattern of the interpolation error δθ withinthe range of the angle data θ=0 to θ and the pattern of theinterpolation error δθ within the range the angle data θ=π to 2π aresymmetrical with respect to θ=π. Accordingly, regarding the correctiondata Δθ for canceling the interpolation error δθ included in theinterpolation data θ′, it is sufficient to store in the correction datastorage unit 4p2 only the correction data Δθ within the range of theinterpolation data θ′=0 to π. Within the range of the interpolation dataθ′=π to 2π, corresponding correction data Δθ can be obtained byutilizing the symmetry with the data stored in the correction datastorage unit 4p2. The quantity of stored correction data can be reducedby limiting the range of the interpolation data θ′ to be stored.

If the error amount of the interpolation error is small, the erroramount and the phase errors Pd can be considered to be substantially inproportion to one another. Accordingly, only correction data for aspecific phase error Pd is stored in advance so that correction data forother phase errors Pd can be obtained by multiplying the correction datafor the specific phase error Pd0 by the percentage of the phase errors.Thus, the phase errors Pd can be limited to reduce the quantity ofcorrection data stored.

The block diagram of FIG. 13 illustrates the configuration of thecorrection data storage unit 4p2 for storing the correction data bylimiting the range of the interpolation data θ′ and the phase errors Pd.In FIG. 13, the correction data storage unit 4p2 comprises an addressconverter circuit 21, correction data table 22, sign inversion selectorcircuit 23, and multiplier circuit 24. The address converter circuit 21receives the interpolation data θ′ and the phase errors Pd and formsaddresses. The correction data table 22 is loaded only with thecorrection data corresponding to combinations of the interpolation dataθ′ in the limited range and the limited phase errors Pd, and thecorrection data are read out from the table 22 in response to addressassignment by the address converter circuit 21. The sign inversionselector circuit 23 inverts the sign of the read correction data inaccordance with the phase errors Pd. The multiplier circuit 24multiplies the correction data by the phase errors Pd.

FIG. 14 is a diagram showing relations between correction data Δθ forthe interpolation error based on the phase errors Pd and theinterpolation data θ′. Referring to FIG. 14, each correction data Δθ hasa size and sign such as to cancel the interpolation error δθ shown inFIG. 12. Since, the correction data Δθ within the range of θ=0 to π issymmetrical with the correction data Δθ within the range of θ=π to 2π,the correction data Δθ within the range of θ=π to 2π can be obtainedfrom the stored corrected data within the range of θ=0 to π.

Further, the correction data Δθ, which changes its size depending on thephase errors Pd, can be considered to be substantially proportional tothe percentage of the phase errors Pd when the phase errors Pd aresmall. The correction data Δθ is stored as a representative value for aspecific phase error Pd, and the other phase errors Pd can be obtainedby multiplication. FIG. 14 illustratively shows cases for Pd=1.0°,Pd=2.0°, and Pd=3.0°. For example, only the correction data Δθ forPd=1.0° is stored, and the correction data for the other phase errors Pdcan be obtained by multiplying the correction data Δθ by the ratio toPd=1.0° as a multiplication factor. Here Pd=0° indicates that there isno phase error between the two encoder signals.

The address converter circuit 21 is a circuit that receives the computedinterpolation data θ′ and the detected phase errors Pd, and formsaddresses for reading out the correction data table 22. In forming theaddresses, the addresses are outputted depending on the range of θ′ andthe sign, positive or negative, of the phase errors Pd, with 0≦θ′<π as aunit, as shown in Table 3 below.

Further, the sign inversion selector circuit 23 does or does not invertthe sign of the data read out from the correction data table 22,depending on the range of the computed interpolation data θ′ and thesign, positive or negative, of the phase errors Pd, as shown in Table 3.

TABLE 3 Address to Sign of Output θ′ Sign of Pd Data Table Data 0 ≦ θ′ <π Positive θ′ Non-inverted Negative π − θ′ Inverted π ≦ θ′ < 2π Positiveθ′ − π Non-inverted Negative 2π − θ′ Inverted

Further, the multiplier circuit 24 is a circuit that multiplies thecorrection data stored for the specific phase error Pd by amultiplication factor of a percentage corresponding to a phase error Pd.Table 4 below shows examples of the multiplication factors. Thecorrection data is stored in advance as a reference for the phase errorPd=1.0°, and correction data for different phase errors Pd are obtainedby multiplication by a specific multiplication factor which isdetermined with reference to the multiplication factor for the phaseerror Pd=1.0°.

TABLE 4 Coefficient of | Pd | Multiplication 0° ≦ | Pd | < 0.5° 0 0.5° ≦| Pd | < 1.5° 1 1.5° ≦ | Pd | < 2.5° 2 2.5° ≦ | Pd | < 3.5° 3 3.5° ≦ |Pd | 4

In the case where the phase error Pd ranges from 1.5° to 2.5°, forexample, the correction data for the phase error Pd=1.0° is multipliedby a multiplication factor of 2. In the case where the phase error Pdranges from 2.5° to 3.5°, the correction data Δθ is obtained bymultiplying the correction data for the phase error Pd=1.0° by amultiplication factor of 3.

In a method of multiplication in the multiplier circuit 24, moreover,the correction data Δθ may be obtained by storing the correction datatable 22 with only correction data for a specific phase error, andmultiplying the read correction data by a factor that is determined bythe ratio of the specific phase error to the detected phase error in thecase where the specific error and the detected phase error have the samesign or multiplying the read correction data by a factor that isdetermined by the ratio of the specific phase error to the detectedphase error and inverting the sign of the product in the case where thespecific error and the detected phase error have different signs.

In a method of multiplication in the multiplier circuit 24, furthermore,the correction data Δθ may be obtained by storing the correction datatable 22 with first correction data for a positive specific phase errorand second correction data for a negative specific phase error,multiplying the correction data read out from the first correction databy a factor determined by the ratio of the positive specific phase errorto the detected phase error when the detected phase error is positive ormultiplying the correction data read out from the second correction databy a factor determined by the ratio of the negative specific phase errorto the detected phase error when the detected phase error is negative.

In the embodiment described above, the signal deviation detecting means(amplitude ratio detecting means or phase error detecting means) isincorporated in the encoder interpolation circuit. Alternatively,however, the signal deviation detecting means may be provided outsidethe encoder interpolation circuit. For example, deviations from a normalwaveform may be detected by fetching encoder signals by means ofexternal synchronization or the like. The result of this detection isapplied to the input of the correction data forming means.

According to the present invention, as described above, theinterpolation error attributable to the amplitude difference and theinterpolation error attributable to the phase error can be reducedduring the generation of interpolation data.

What is claimed is:
 1. An encoder interpolation circuits comprising: aninterpolative computation unit receiving two encoder signals ofdifference phases, carrying out interpolative computation for thesesignals and outputting interpolation angle data; a correction dataforming unit obtaining and outputting correction data corresponding to acombination of a detected deviation of the two encoder signals from anormal waveform and the interpolation angle data outputted from saidinterpolative computation unit; and a corrective computation unitcorrecting the interpolation angle data outputted from saidinterpolative computation unit with the correction data outputted fromsaid correction data forming unit and outputting corrected interpolationangle data.
 2. An encoder interpolation circuit according to claim 1,wherein said correction data forming unit forms the correction data byinputting the interpolation angle data and said detected deviation ofthe two encoder signals individually into variables of a computationalexpression for obtaining correction data, and operating thecommunicational expression.
 3. An encoder interpolation circuitcomprising: an interpolative computation unit receiving two encodersignals of difference phases, carrying out interpolative computation forthese signals and outputting interpolation angle data; a correction dataforming unit obtaining and outputting correction data corresponding to acombination of a detected deviation of the two encoder signals from anormal waveform and the interpolation angle data outputted from saidinterpolative computation unit; and a corrective computation unitcorrecting the interpolation angle data outputted from saidinterpolative computation unit with the correction data outputted fromsaid correction data forming unit and outputting corrected interpolationangle data, wherein said correction data forming unit is previouslystored with the value of correction data for a combination of the outputof said interpolative computation unit and the output of said correctiondata forming unit, and said correction data forming unit receives theoutput of the interpolative computation unit and the output of thecorrection data forming unit and outputs the previously stored value ofthe correction data corresponding to the combination of these outputs.4. An encoder interpolation circuit according to claim 3, wherein saidcorrection data stored in said correction data forming unit can befetched with an address which represents a combination of the output ofsaid interpolative computation unit and the output of said correctiondata forming unit.
 5. An encoder interpolation circuit according toclaim 3, wherein said correction data forming unit is stored with a datatable so that corresponding data can be fetched with an address whichrepresents a combination of angle data in a limited range and a detectedsignal deviation, and said correction data forming unit receives thedetected deviation of the two encoder signals and the output of theinterpolative computation determines an address based on the deviationand the output, and forms said correction data by accessing said datatable to fetch the corresponding data with the determined address andprocessing the fetched data.
 6. An encoder interpolation circuitaccording to claim 3, wherein said correction data forming unit isstored with correction data corresponding to a reference signaldeviation value and angle data in a limited range, and said correctiondata forming unit forms said correction data by receiving the detecteddeviation of the two encoder signals and output of the interpolativecomputation unit, fetches corresponding data from said stored correctiondata based on the output and the deviation, and carrying out processingincluding processing in accordance with of the relation between saidreference signal deviation value and said detected signal deviation. 7.An encoder interpolation circuit comprising: an interpolativecomputation unit receiving two encoder signals of difference phases,carrying out interpolative computation for these signals and outputtinginterpolation angle data; a correction data forming unit obtaining andoutputting correction data corresponding to a combination of a detecteddeviation of the two encoder signals from a normal waveform and theinterpolation angle data outputted from said interpolative computationunit; and a corrective computation unit correcting the interpolationangle data outputted from said interpolative computation unit with thecorrection data outputted from said correction data forming unit andoutputting corrected interpolation angle data, wherein said deviation ofthe two encoder signals is the ratio of the amplitude of one sine-waveencoder signal to the amplitude of the other sine-wave encoder signal.8. An encoder interpolation circuit according to claim 7, wherein saidcorrection data forming unit forms the correction data by substitutingan output of said interpolative computation unit and a detectedamplitude ratio, as a detected deviation of the two encoder signalsindividually for variables in a predetermined computational expressionfor obtaining correction data and operating the communicationalexpression.
 9. An encoder interpolation circuit according to claim 7,wherein said correction data forming unit is stored with data in a tableform capable of being fetched with an address representing a combinationof the amplitude ratio and the angle data, and said correction dataforming unit determines said address based on the received deviation ofthe two encoder signals and the output of the interpolative computationunit, fetches data from said table according to the determined address,and outputs the correction data based on the fetched data.
 10. Anencoder interpolation circuit according to claim 9, wherein said angledata constituting said address ranges from 0 to π/2.
 11. An encoderinterpolation circuit according to claim 9, wherein said correction dataforming unit stores first correction data for a specific amplitude ratiok1 in the case where the amplitude of one encoder signal is greater thanthe amplitude of the other encoder signal and second correction data fora specific amplitude ratio k2 in the case where the amplitude of the oneencoder signal is smaller than the amplitude of the other encodersignal, and multiplies the first correction data by (1−k)/(1−k1) whenthe detected amplitude ratio k is higher than 1 or multiplies the secondcorrection data by (1−k)/(1−k2) when the detected amplitude ratio k islower than
 1. 12. An encoder interpolation circuit according to claim 9,wherein said correction data forming unit stores only correction datafor a specific amplitude ratio k1 in the case where the amplitude of oneencoder signal is greater than the amplitude of the other encodersignal, and multiplies the first correction data by (1−k)/(1−k1) whenthe detected amplitude ratio k is higher than 1 or multiplies thecorrection data by −(1−k)/(1−k1) when the detected amplitude ratio k islower than
 1. 13. An encoder interpolation circuit according to claim 1,wherein said deviation of the two encoder signals is a phase error asthe difference between the predetermined phase difference between twoencoder signals and an actual phase difference between the two encodersignals.
 14. An encoder interpolation circuit according to claim 13,wherein said correction data forming unit forms the correction data bysubstituting an output of said interpolative computation unit and adetected phase error, as a deviation of the two encoder signals,individually for variables in a computational expression for obtainingpreset correction data and operating the computational expression. 15.An encoder interpolation circuit according to claim 13, wherein saidcorrection data forming unit is stored with data in a table form capableof being fetched with an address representing a combination of saidphase error and the angle data, and said correction data forming unitdetermines said address based on the received phase error, as thedeviation of the two encoder signals, and output of the interpolativecomputation unit, fetches data from said table according to thedetermined address, and outputs the correction data based on the fetcheddata.
 16. An encoder interpolation circuit according to claim 15,wherein said predetermined phase difference between two encoder signalsis π/2, and said angle data constituting said address ranges from 0 toπ.
 17. An encoder interpolation circuit according to claim 15, whereinsaid correction data forming unit stores first correction data for apositive specific phase error and second correction data for a negativespecific phase error, and multiplies the first correction data by afactor determined by the positive specific phase error and the detectedphase error in the case where the detected phase error is positive ormultiplies the second correction data by a factor determined by thenegative specific phase error and the detected phase error in the casewhere the detected phase error is negative.
 18. An encoder interpolationcircuit according to claim 15, wherein said correction data forming unitstores only correction data for a specific phase error, and multipliesthe read correction data by a factor determined by the specific phaseerror and the detected phase error in the case where the specific errorand the detected phase error have the same sign or multiplies the readcorrection data by a factor determined by the specific phase error andthe detected phase error in the case where the specific error and thedetected phase error have different signs and inverts the sign.